This invention relates to an LSI circuit with a built-in circuit to facilitate the self-checking function of the LSI circuit.
Recent achievements in the LSI field have been remarkable and are moving toward ever-increasing integration and complication. Especially, a custom-made LSI circuit, in particular, a gate array, which system designers can easily develop, has recently been in the spotlight and is going in a practical phase.
The gate array normally needs numerous test data to check the functions of its internal circuits, which results in lengthy testing. Various testing measures have therefore been developed for the problem.
FIG. 1 illustrates an LSI circuit with no function for producing testing data. Such an LSI circuit requires test data for every test conducted; the test data for checking the function of the internal circuits of the LSI circuit mounts up to a considerably large quantity. It is also actually impossible to prepare test data to cope with every foreseeable case.
FIG. 2 illustrates a system which comprises a psuedorandom data generator (PID-GEN) 3, using a linear feedback register and an output data compressor 4. When testing circuit functions, the system permits a switching circuit 5 to selectively switch the data flow from an ordinary input line to that from the psuedorandom data generator 3, supplies the selected data to an internal logic circuit 11, and then checks a signal output SO from the output data compressor 4. The prior art system automatically generates input data with a speed intrinsic to an LSI circuit, so that it achieves the test even with a large quantity of data at a higher speed. According to the prior art, however, because the data supplied from the psuedorandom data generator 3 always includes data that is not required to operate the LSI circuit, unnecessary tests are inevitably performed.
When many flip-flops are used in the internal circuits of an LSI circuit, the prior art system is also not effective in testing the circuit functions because even in execution of ordinary operations of the LSI circuit, desired logic operations cannot be carried out without entry of a specific stream of data.
FIG. 3 shows a means known to solve the problem. This means combines the system shown in FIG. 1 and the so-called scan system, which is representative of the IBM LSS (Level Sensitive Scan). The scan system has its internal flip-flops coupled to constitute a shift register and further has a SCANIN pin and a SCANOUT pin. After specific data is loaded in the flip-flop-based shift register through the path, which starts from the SCANIN pin and ends at the SCANOUT pin, the scan system reads out the output of the shift register from the SCANOUT pin for a functional check on an LSI circuit. The system illustrated in FIG. 3 allows the scan system to input specific data to a control flip-flop 7 in an internal logic circuit 6, executes logic operations using the output of a psuedorandom data generator (PID-GEN) 8, and then observes, as does the system of FIG. 2, a signal output SO from an output data compressor 9.
FIG. 4 exemplifies the configuration of the psuedorandom data generator 8; FIG. 5, the structure of the output data compressor 9. Both of these devices are constituted by flip-flops and exclusive gates.
Because the system of FIG. 3 is designed for nothing more than the detection of a functional failure in a circuit, however, it cannot be guaranteed that the combination of intended functions is properly running. The most desired operation would be to carry out the detection while performing the functions of an LSI circuit as specified. This operation is especially important for checking designed circuits.